In the manufacturing of a thin film transistor-liquid crystal display (TFT-LCD), there is a trend of substituting a 5Mask process with a 4Mask process. The 4Mask process, in which a half-exposure technology is used, has notable advantages of reducing production period and improving yield. However, in the case that the half-exposure technology is utilized for performing exposure of a channel region, problems such as poor channel characteristics may appear during practical production, which are almost inevitable in the 4Mask process. In the 4Mask process, different from the 5Mask process, an active layer and a source/drain layer are exposed at the same time, and the half-exposure technology is performed so as to form a channel region of the active layer. The current half-exposure technology applies a partial light-blocking structure, which is formed as a slit in a grid shape or in a mesh shape, to the channel region mask structure, so as to control the half-exposure of the photoresist on the channel region.
FIG. 1 is a schematic view showing a half-exposure mask for a channel region provided on a gate line and a gate electrode in the conventional technology. As shown in FIG. 1, in order to form the pattern for the channel region of a TFT over the gate line and the gate electrode 4, the half-exposure mask comprises a channel region half-exposure mask structure 1, a drain mask structure 2, and a source mask structure 3.
FIG. 2 is a top view showing the photoresist pattern in the channel region after exposure and development with the half-exposure mask. As shown in FIG. 2, the photoresist pattern in the channel region after exposure and development comprises a drain photoresist 6, the channel region photoresist 7, and the source photoresist 8, which are formed on a source/drain metal layer 9.
FIG. 3A is a cross-sectional view taken along a line A-A in FIG. 2, and FIG. 3B is a cross-sectional view taken along a line B-B in FIG. 2. As shown in FIGS. 3A and 3B, a gate insulting layer 14 is formed on the gate line and the gate electrode 4, an active layer 12 is formed on the gate insulting layer 14, the source/drain metal layer 9 is formed on the active layer 12, and the exposed photoresist pattern is formed on the source/drain metal layer 9. The thickness of the channel region photoresist 7 in the half exposed region is smaller than that in the non-exposed region (corresponding to the drain photoresist 6 and the source photoresist 8), but larger than that in the fully exposed region (corresponding to a portion where the source/drain metal layer 9 is exposed).
FIG. 4 is a top view showing the channel region after etching with a half-exposure mask. As shown in FIG. 4, the channel region after etching comprises an exposed active layer 12 in the channel region, and a pattern of the formed a source 13 and a drain 11.
During practical production, due to the non-uniformity in the thickness of the photoresist and in the half-exposure, as well as the interference between the half exposed portion and the fully exposed portion during exposure, the thickness of the half exposed portion at a boundary region is reduced. Therefore, the processes following the exposure, such as wet etching, dry etching, cleaning, etc., very possibly bring about destruction such as damage or under-etching to a portion of the photoresist in connection with the active layer around the channel region, the source/drain metal electrode, etc. For example, there may be bad characteristics such as a disconnection, as shown FIG. 5. Such destructions certainly destruct the active layer in the channel region in turn, thus adversely influencing the electric characteristics of the pixel. At present, there is still no practical countermeasure thereto during production, and substantial economic loss has been caused.